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80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR
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Product Features
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Pin/Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture --One Instruction/Clock Execution --Core Clock Rate is: 80960JA/JF 1x the Bus Clock 80960JD 2x the Bus Clock 80960JT 3x the Bus Clock --Load/Store Programming Model --Sixteen 32-Bit Global Registers --Sixteen 32-Bit Local Registers (8 sets) --Nine Addressing Modes --User/Supervisor Protection Model Two-Way Set Associative Instruction Cache --80960JA - 2 Kbyte --80960JF/JD - 4 Kbyte --80960JT - 16 Kbyte --Programmable Cache-Locking Mechanism Direct Mapped Data Cache --80960JA - 1 Kbyte --80960JF/JD - 2 Kbyte --80960JT - 4 Kbyte --Write Through Operation On-Chip Stack Frame Cache --Seven Register Sets Can Be Saved --Automatic Allocation on Call/Return --0-7 Frames Reserved for High-Priority Interrupts
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On-Chip Data RAM --1 Kbyte Critical Variable Storage --Single-Cycle Access 3.3 V Supply Voltage --5 V Tolerant Inputs --TTL Compatible Outputs High Bandwidth Burst Bus --32-Bit Multiplexed Address/Data --Programmable Memory Configuration --Selectable 8-, 16-, 32-Bit Bus Widths --Supports Unaligned Accesses --Big or Little Endian Byte Ordering High-Speed Interrupt Controller --31 Programmable Priorities --Eight Maskable Pins plus NMI --Up to 240 Vectors in Expanded Mode Two On-Chip Timers --Independent 32-Bit Counting --Clock Prescaling by 1, 2, 4 or 8 --lnternal Interrupt Sources Halt Mode for Low Power IEEE 1149.1 (JTAG) Boundary Scan Compatibility Packages --132-Lead Pin Grid Array (PGA) --132-Lead Plastic Quad Flat Pack (PQFP) --196-Ball Mini Plastic Ball Grid Array (MPBGA)
Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273159-001 March, 1998
80960JA/JF/JD/JT 3.3 V Microprocessor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960JA/JF/JD/JT 3.3 V Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
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80960JA/JF/JD/JT 3.3 V Microprocessor
Contents
1.0 2.0 Introduction .................................................................................................................. 7 80960Jx Overview ...................................................................................................... 7
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 80960 Processor Core .......................................................................................... 9 Burst Bus.............................................................................................................10 Timer Unit............................................................................................................10 Priority Interrupt Controller ..................................................................................10 Instruction Set Summary .....................................................................................11 Faults and Debugging .........................................................................................11 Low Power Operation..........................................................................................11 Test Features ......................................................................................................12 Memory-Mapped Control Registers ....................................................................12 Data Types and Memory Addressing Modes ......................................................12 Pin Descriptions ..................................................................................................16 3.1.1 Functional Pin Definitions.......................................................................16 3.1.2 80960Jx 132-Lead PGA Pinout..............................................................22 3.1.3 80960Jx 132-Lead PQFP Pinout............................................................26 3.1.4 80960Jx 196-Ball MPBGA Pinout ..........................................................29 Package Thermal Specifications .........................................................................34 Thermal Management Accessories.....................................................................38 3.3.1 Heatsinks................................................................................................38 Absolute Maximum Ratings.................................................................................39 Operating Conditions...........................................................................................39 Connection Recommendations ...........................................................................40 VCC5 Pin Requirements (VDIFF) .......................................................................40 VCCPLL Pin Requirements.................................................................................41 DC Specifications ................................................................................................42 AC Specifications ................................................................................................44 4.7.1 AC Test Conditions and Derating Curves ..............................................47 4.7.2 AC Timing Waveforms ...........................................................................52 Basic Bus States .................................................................................................68 Boundary-Scan Register .....................................................................................69
3.0
Package Information...............................................................................................14
3.1
3.2 3.3
4.0
Electrical Specifications........................................................................................39
4.1 4.2 4.3 4.4 4.5 4.6 4.7
5.0
Bus Functional Waveforms..................................................................................58
5.1 5.2
6.0 7.0
Device Identification ...............................................................................................74 Revision History .......................................................................................................77
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Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 80960Jx Microprocessor Package Options...........................................................7 80960Jx Block Diagram ........................................................................................9 132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22 132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23 132-Lead PQFP - Top View ................................................................................26 196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up ..................29 196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30 VCC5 Current-Limiting Resistor ..........................................................................40 VCCPLL Lowpass Filter ......................................................................................41 AC Test Load ......................................................................................................47 Output Delay or Hold vs. Load Capacitance .......................................................48 TLX vs. AD Bus Load Capacitance......................................................................48 80960JA/JF ICC Active (Power Supply) vs. Frequency .......................................49 80960JA/JF ICC Active (Thermal) vs. Frequency ................................................49 80960JD ICC Active (Power Supply) vs. Frequency............................................50 80960JD ICC Active (Thermal) vs. Frequency.....................................................50 80960JT ICC Active (Power Supply) vs. Frequency ...........................................51 80960JT ICC Active (Thermal) vs. Frequency .....................................................51 CLKIN Waveform ................................................................................................52 TOV1 Output Delay Waveform .............................................................................52 TOF Output Float Waveform................................................................................53 TIS1 and TIH1 Input Setup and Hold Waveform ...................................................53 TIS2 and TIH2 Input Setup and Hold Waveform ...................................................53 TIS3 and TIH3 Input Setup and Hold Waveform ...................................................54 TIS4 and TIH4 Input Setup and Hold Waveform ...................................................54 TLX, TLXL and TLXA Relative Timings Waveform.................................................55 DT/R and DEN Timings Waveform .....................................................................55 TCK Waveform....................................................................................................56 TBSIS1 and TBSIH1 Input Setup and Hold Waveforms .........................................56 TBSOV1 and TBSOF1 Output Delay and Output Float Waveform..........................56 TBSOV2 and TBSOF2 Output Delay and Output Float Waveform..........................57 TBSIS2 and TBSIH2 Input Setup and Hold Waveform ...........................................57 Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58 Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................59 Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60 Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................61 Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus .....................................................................62 Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian .................................................63 HOLD/HOLDA Waveform For Bus Arbitration ....................................................64 Cold Reset Waveform .........................................................................................65 Warm Reset Waveform .......................................................................................66 Entering the ONCE State ....................................................................................67 Bus States with Arbitration ..................................................................................68 Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72 Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73 80960JT Device Identification Register...............................................................74 80960JD Device Identification Register ..............................................................75 80960JA/JF Device Identification Register .........................................................76
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Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 80960Jx Instruction Set.......................................................................................13 Pin Description Nomenclature.............................................................................16 Pin Description -- External Bus Signals .............................................................17 Pin Description -- Processor Control Signals, Test Signals and Power .............20 Pin Description -- Interrupt Unit Signals .............................................................21 132-Lead PGA Pinout -- In Signal Order............................................................24 132-Lead PGA Pinout -- In Pin Order ................................................................25 132-Lead PQFP Pinout -- In Signal Order .........................................................27 132-Lead PQFP Pinout -- In Pin Order ..............................................................28 196-Ball MPBGA Pinout -- In Signal Order ........................................................31 196-Ball MPBGA Pinout -- In Pin Order .............................................................33 132-Lead PGA Package Thermal Characteristics...............................................35 196-Ball MPBGA Package Thermal Characteristics ...........................................35 132-Lead PQFP Package Thermal Characteristics ............................................36 Maximum TA at Various Airflows in C (80960JT) ...............................................36 Maximum TA at Various Airflows in C (80960JD) ..............................................37 Maximum TA at Various Airflows in C (80960JA/JF)..........................................37 Absolute Maximum Ratings.................................................................................39 80960Jx Operating Conditions ............................................................................39 VDIFF Parameters ..............................................................................................40 80960Jx DC Characteristics................................................................................42 80960Jx ICC Characteristics................................................................................42 80960Jx AC Characteristics ................................................................................44 Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) ...................47 Boundary-Scan Register Bit Order......................................................................69 Natural Boundaries for Load and Store Accesses ..............................................70 Summary of Byte Load and Store Accesses.......................................................70 Summary of Short Word Load and Store Accesses............................................70 Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)...........................71 80960Jx Device Type and Stepping Reference ..................................................74 Fields of 80960JT Device ID ...............................................................................75 80960JT Device ID Model Types ........................................................................75 Fields of 80960JD Device ID...............................................................................76 80960JD Device ID Model Types........................................................................76 Fields of 80960JA/JF Device ID ..........................................................................77 80960JA/JF Device ID Model Types ...................................................................77 Data Sheet Revision History ...............................................................................77
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80960JA/JF/JD/JT 3.3 V Microprocessor
1.0
Introduction
This document contains information for the 80960Jx microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions -- other than parametric performance -- are published in the i960(R) Jx Microprocessor Developer's Manual (272483).
Figure 1.
80960Jx Microprocessor Package Options
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A80960JX
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(c) 19xx
i960
(R)
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GD80960JX XXXXXXXSS M (c) 19xx
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132-Pin PGA
NG80960JX
XXXXXXXX SS
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(c) 19xx
136-Ball MPBGA
132-Pin PQFP
Throughout this data sheet, references to "80960Jx" indicate features that apply to all of the following:
* 80960JA -- 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache * 80960JF -- 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache * 80960JD -- 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock
doubling
* 80960JT -- 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock
tripling
2.0
80960Jx Overview
The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx is object code compatible with the 80960 Core Architecture and is capable of sustained execution at the rate of one instruction per clock. This processor's features include generous instruction cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable timer units. The 80960Jx's clock multiplication operates the processor core at two or three times the bus clock rate to improve execution performance without increasing the complexity of board designs. Memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU execution from the external bus.
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80960JA/JF/JD/JT 3.3 V Microprocessor
The 80960Jx rapidly allocates and deallocates local register sets during context switches. The processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960Jx to external components. The user programs physical and logical memory attributes through memory-mapped control registers (MMRs) -- an extension not found on the i960 Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model. This processor integrates two important peripherals: a timer unit, and an interrupt controller. These and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar 80960 architecture. The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. These operate in either single-shot or auto-reload mode and can generate interrupts. The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts. The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, the ICU compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. The ICU also supports the integrated timer interrupts. The 80960Jx features a Halt mode designed to support applications where low power consumption is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. The 80960Jx's testability features, including ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG), provide a powerful environment for design debug and fault diagnosis. The Solutions960(R) program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.
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80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 2.
80960Jx Block Diagram
Physical Region Configuration Bus Control Unit Bus Request Queues Control 21 Address/ Data Bus 32
CLKIN
PLL, Clocks, Power Mgmt
32-bit buses address / data
Instruction Cache 80960JA - 2K 80960JF/JD - 4K
TAP 5
Boundary Scan Controller
80960JT - 16K
Two-Way Set Associative
Instruction Sequencer
Constants Control
Two 32-Bit Timers Interrupt Port Programmable Interrupt Controller 9 Memory-Mapped Register Interface
8-Set Local Register Cache Multiply Divide Unit Execution and Address Generation Unit
effective address SRC1 SRC2 SRC1 SRC2 DEST DEST
Memory Interface Unit
128 Global / Local Register File
SRC1 SRC2 DEST
32-bit Address 32-bit Data SRC1 DEST
1K Data RAM
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Direct Mapped Data Cache 80960JA - 1K 80960JF/JD - 2K 80960JT - 4K
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this processor core as a very high performance device that is also cost-effective. Factors that contribute to the core's performance include:
* * * * * * * * * *
Core operates at the bus speed with the 80960JA/JF Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively Single-clock execution of most instructions Independent Multiply/Divide Unit Efficient instruction pipeline minimizes pipeline break latency Register and resource scoreboarding allow overlapped instruction execution 128-bit register bus speeds local register caching Two-way set associative, integrated instruction cache Direct-mapped, integrated data cache 1 Kbyte integrated data RAM delivers zero wait state program data
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2.2
Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed. Users may configure the 80960Jx's bus controller to match an application's fundamental memory organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and data caching are programmed through a group of logical memory templates and a defaults register. The BCU's features include:
* * * * * *
Multiplexed external bus to minimize pin count 32-, 16- and 8-bit bus widths to simplify I/O interfaces External ready control for address-to-data, data-to-data and data-to-next-address wait state types Support for big or little endian byte ordering to facilitate the porting of existing program code Unaligned bus accesses performed transparently Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record (IBR). The user may examine the contents of the caches by executing special cache control instructions.
2.3
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the TU registers. These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960Jx's interrupt controller. The TU can generate a fault when unauthorized writes from user mode are detected. Clock prescaling is supported.
2.4
Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channels and a single Non-Maskable Interrupt (NMI) pin. Interrupts are serviced according to their priority levels relative to the current process priority. Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
* * * *
Interrupt vectors and interrupt handler routines can be reserved on-chip Register frames for high-priority interrupt handlers can be cached on-chip The interrupt stack can be placed in cacheable memory space Interrupt microcode executes at two or three times the bus frequency for the 80960JD and 80960JT respectively
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2.5
Instruction Set Summary
The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:
* * * * * * *
Conditional Move Conditional Add Conditional Subtract Byte Swap Halt Cache Control Interrupt Control
Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960(R) Jx Microprocessor Developer's Manual (272483) for a detailed description of each instruction.
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor's sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. The processor also uses dynamic power management to turn off clocks to unused circuits. Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. Processor execution resumes from internally or externally generated interrupts.
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2.8
Test Features
The 80960Jx incorporates numerous features which enhance the user's ability to test both the processor and the system to which it is attached. These features include ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG). The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to electrically "remove" itself from a circuit board. This allows for system-level testing where a remote tester -- such as an in-circuit emulator -- can exercise the processor system. The provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board. The JTAG Boundary Scan feature is an attractive alternative to conventional "bed-of-nails" testing. It can examine connections which might otherwise be inaccessible to a test system.
2.9
Memory-Mapped Control Registers
The 80960Jx, though compliant with i960 series processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These give software the interface to easily read and modify internal control registers. Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished through regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles.
2.10
Data Types and Memory Addressing Modes
As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:
* * * * * * * * * *
Bit Bit fields Integer (8-, 16-, 32-, 64-bit) Ordinal (8-, 16-, 32-, 64-bit unsigned integers) Triple word (96 bits) Quad word (128 bits)
The 80960Jx provides a full set of addressing modes for C and assembly programming: Two Absolute modes Five Register Indirect modes Index with displacement IP with displacement
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Table 1.
80960Jx Instruction Set
Data Movement Add Subtract Multiply Divide Remainder Load Store Move *Conditional Select Load Address Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry *Conditional Add *Conditional Subtract Rotate Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Processor Management Flush Local Registers Modify Arithmetic Controls Modify Trace Controls Mark Force Mark Modify Process Controls *Halt System Control *Cache Control *Interrupt Control
Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.
Arithmetic
Logical
Bit, Bit Field and Byte
And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand
Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal *Byte Swap
Branch Call Unconditional Branch Conditional Branch Compare and Branch
Call/Return
Fault
Call Extended Call System Return Branch and Link Atomic
Conditional Fault Synchronize Faults
Atomic Add Atomic Modify
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3.0
Package Information
The 80960Jx is offered with four speeds and three package types. The 132-pin Pin Grid Array (PGA) device is specified for operation at VCC = 3.3 V 0.15 V over a case temperature range of 0 to 100C:
* * * * * * * * *
A80960JT-100 (100 MHz core, 33 MHz bus) A80960JT-75 (75 MHz core, 25 MHz bus) A80960JD-66 (66 MHz core, 33 MHz bus) A80960JD-50 (50 MHz core, 25 MHz bus) A80960JD-40 (40 MHz core, 20 MHz bus) A80960JD-33 (33 MHz core, 16 MHz bus) A80960JA/JF-33 (33 MHz) A80960JA/JF-25 (25 MHz) A80960JA/JF-16 (16 MHz)
The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at VCC = 3.3 V 0.15 V over a case temperature range of 0 to 100C:
* * * * * * * * *
NG80960JT-100 (100 MHz core, 33 MHz bus) NG80960JT-75 (75 MHz core, 25 MHz bus) NG80960JD-66 (66 MHz core, 33 MHz bus) NG80960JD-50 (50 MHz core, 25 MHz bus) NG80960JD-40 (40 MHz core, 20 MHz bus) NG80960JD-33 (33 MHz core, 16 MHz bus) NG80960JA/JF-33 (33 MHz) NG80960JA/JF-25 (25 MHz) NG80960JA/JF-16 (16 MHz)
An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation at VCC = 3.3 V 0.15 V over a case temperature range of -40 to 100C:
* TG80960JA-25 (25 MHz)
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The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at VCC = 3.3 V 0.15 V over a case temperature range of 0 to 100C:
* * * * * * * *
GD80960JT-100 (100 MHz core, 33 MHz bus) GD80960JT-75 (75 MHz core, 25 MHz bus) GD80960JD-50 (50 MHz core, 25 MHz bus) GD80960JD-40 (40 MHz core, 20 MHz bus) GD80960JD-33 (33 MHz core, 16 MHz bus) GD80960JA/JF-33 (33 MHz) GD80960JA/JF-25 (25 MHz) GD80960JA/JF-16 (16 MHz)
For package specifications and information, refer to Intel's Packaging Handbook (240800).
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3.1
Pin Descriptions
This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA) package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid Array (MPBGA). Section 3.1.1, "Functional Pin Definitions", describes pin function; Section 3.1.2, "80960Jx 132-Lead PGA Pinout", Section 3.1.3, "80960Jx 132-Lead PQFP Pinout" and Section 3.1.4, "80960Jx 196-Ball MPBGA Pinout", define the signal and pin locations for the supported package types.
3.1.1
Functional Pin Definitions
Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with the bus interface are described in Table 3. Pins associated with basic control and test functions are described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.
Table 2.
Pin Description Nomenclature
Symbol I O I/O - S Input pin only. Output pin only. Pin can be either an input or output. Pin must be connected as described. Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation. S(E) Edge sensitive input S(L) Level sensitive input Asynchronous. Inputs may be asynchronous relative to CLKIN. A (...) A(E) Edge sensitive input A(L) Level sensitive input While the processor's RESET pin is asserted, the pin: R (...) R(1) is driven to VCC R(0) is driven to VSS R(Q) is a valid output R(X) is driven to unknown state R(H) is pulled up to VCC While the processor is in the hold state, the pin: H (...) H(1) is driven to VCC H(0) is driven to VSS H(Q) Maintains previous state or continues to be a valid output H(Z) Floats While the processor is halted, the pin: P (...) P(1) is driven to VCC P(0) is driven to VSS P(Q) Maintains previous state or continues to be a valid output Description
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Table 3.
Pin Description -- External Bus Signals (Sheet 1 of 3)
NAME TYPE DESCRIPTION ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data to and from memory. During an address (Ta) cycle, bits 31:2 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write data is present on one or more contiguous bytes, comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations, unused pins are driven to determinate values. SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the number of data transfers during the bus transaction. AD31:0 I/O S(L) R(X) H(Z) P(Q) AD1 0 0 1 1 AD0 0 1 0 1 Bus Transfers 1 Transfer 2 Transfers 3 Transfers 4 Transfers
When the processor enters Halt mode, if the previous bus operation was a: * write -- AD31:2 are driven with the last data value on the AD bus. * read -- AD31:4 are driven with the last address value on the AD bus; AD3:2 are driven with the value of A3:2 from the last data cycle. Typically, AD1:0 reflect the SIZE information of the last bus transaction (either instruction fetch or load/store) that was executed before entering Halt mode. O R(0) H(Z) P(0) O R(1) H(Z) P(1) O R(1) H(Z) P(1) ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active HIGH and floats to a high impedance state during a hold cycle (Th). ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility with existing 80960Kx systems. ADDRESS STROBE indicates a valid address and the start of a new bus access. The processor asserts ADS for the entire Ta cycle. External bus control logic typically samples ADS at the end of the cycle. ADDRESS3:2 comprise a partial demultiplexed address bus. O R(X) H(Z) P(Q)
ALE
ALE
ADS
32-bit memory accesses: the processor asserts address bits A3:2 during Ta. The partial word address increments with each assertion of RDYRCV during a burst. 16-bit memory accesses: the processor asserts address bits A3:1 during Ta with A1 driven on the BE1 pin. The partial short word address increments with each assertion of RDYRCV during a burst. 8-bit memory accesses: the processor asserts address bits A3:0 during Ta, with A1:0 driven on BE1:0. The partial byte address increments with each assertion of RDYRCV during a burst.
A3:2
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17
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description -- External Bus Signals (Sheet 2 of 3)
NAME TYPE DESCRIPTION BYTE ENABLES select which of up to four data bytes on the bus participate in the current bus access. Byte enable encoding is dependent on the bus width of the memory region accessed:
BE3:0
O R(1) H(Z) P(1)
32-bit bus: BE3 enables data on AD31:24 BE2 enables data on AD23:16 BE1 enables data on AD15:8 BE0 enables data on AD7:0 16-bit bus: BE3 becomes Byte High Enable (enables data on AD15:8) BE2 is not used (state is high) BE1 becomes Address Bit 1 (A1) BE0 becomes Byte Low Enable (enables data on AD7:0) 8-bit bus: BE3 is not used (state is high) BE2 is not used (state is high) BE1 becomes Address Bit 1 (A1) BE0 becomes Address Bit 0 (A0) The processor asserts byte enables, byte high enable and byte low enable during Ta. Since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst. They remain active through the last Td cycle. For accesses to 8- and 16-bit memory, the processor asserts the address bits in conjunction with A3:2 described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus transaction:
WIDTH/ HLTD1:0
O R(0) H(Z) P(1)
WIDTH/HLTD1 0 0 1 1
WIDTH/HLTD0 0 1 0 1 8 Bits Wide 16 Bits Wide 32 Bits Wide Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in response to a HOLD request, regardless of prior operating state. O R(X) H(Z) P(Q) O R(0) H(Z) P(Q) O R(0) H(Z) P(Q) DATA/CODE indicates that a bus access is a data access (1) or an instruction access (0). D/C has the same timing as W/R. 0 = instruction access 1 = data access WRITE/READ specifies, during a Ta cycle, whether the operation is a write (1) or read (0). It is latched on-chip and remains valid during Td cycles. 0 = read 1 = write DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta and Tw/Td cycles for a write. DT/R never changes state when DEN is asserted. 0 = receive 1 = transmit DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. DEN is used with DT/R to provide control for data transceivers connected to the data bus. 0 = data cycle 1 = not data cycle
D/C
W/R
DT/R
DEN
O R(1) H(Z) P(1)
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3.
Pin Description -- External Bus Signals (Sheet 3 of 3)
NAME TYPE DESCRIPTION BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last data transfer of burst and non-burst accesses. BLAST remains active as long as wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final data transfer in a bus cycle. 0 = last data transfer 1 = not last data transfer READY/RECOVER indicates that data on AD lines can be sampled or removed. If RDYRCV is not asserted during a Td cycle, the Td cycle is extended to the next cycle by inserting a wait state (Tw). I S(L) 0 = sample data 1 = don't sample data The RDYRCV pin has another function during the recovery (Tr) state. The processor continues to insert additional recovery states until it samples the pin HIGH. This function gives slow external devices more time to float their buffers before the processor begins to drive address again. 0 = insert wait states 1 = recovery complete BUS LOCK indicates that an atomic read-modify-write operation is in progress. The LOCK output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. The processor does not grant HOLDA while it is asserting LOCK. This prevents external agents from accessing memory involved in semaphore operations. LOCK/ ONCE I/O S(L) R(H) H(Z) P(1) 0 = Atomic read-modify-write in progress 1 = Atomic read-modify-write not in progress ONCE MODE: The processor samples the ONCE input during reset. If it is asserted LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the processor stops all clocks and floats all output pins. The pin has a weak internal pullup which is active during reset to ensure normal operation when the pin is left unconnected. 0 = ONCE mode enabled 1 = ONCE mode not enabled HOLD: A request from an external bus master to acquire the bus. When the processor receives HOLD and grants bus control to another master, it asserts HOLDA, floats the address/data and control lines and enters the Th state. When HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or Ta state, resuming control of the address/data and control lines. 0 = no hold request 1 = hold request O R(Q) H(1) P(Q) HOLD ACKNOWLEDGE indicates to an external bus master that the processor has relinquished control of the bus. The processor can grant HOLD requests and enter the Th state during reset and while halted as well as during regular operation. 0 = hold not acknowledged 1 = hold acknowledged BUS STATUS indicates that the processor may soon stall unless it has sufficient access to the bus; see i960(R) Jx Microprocessor Developer's Manual (272483). Arbitration logic can examine this signal to determine when an external bus master should acquire/relinquish the bus. 0 = no potential stall 1 = potential stall
BLAST
O R(1) H(Z) P(1)
RDYRCV
HOLD
I S(L)
HOLDA
BSTAT
O R(0) H(Q) P(0)
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19
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 4.
Pin Description -- Processor Control Signals, Test Signals and Power
NAME CLKIN TYPE I DESCRIPTION CLOCK INPUT provides the processor's fundamental time base; both the processor core and the external bus run at the CLKIN rate. All input and output timings are specified relative to a rising CLKIN edge. RESET initializes the processor and clears its internal logic. During reset, the processor places the address/data bus and control output pins in their idle (inactive) states. RESET I A(L) During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST and HOLD. The RESET pin has an internal synchronizer. To ensure predictable processor initialization during power up, RESET must be asserted a minimum of 10,000 CLKIN cycles with VCC and CLKIN stable. On a warm reset, RESET should be asserted for a minimum of 15 cycles. SELF TEST enables or disables the processor's internal self-test feature at initialization. STEST is examined at the end of reset. When STEST is asserted, the processor performs its internal self-test and the external bus confidence test. When STEST is deasserted, the processor performs only the external bus confidence test. 0 = self test disabled 1 = self test enabled FAIL indicates a failure of the processor's built-in self-test performed during initialization. FAIL is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests: * When self-test passes, the processor deasserts FAIL and begins operation from user code. * When self-test fails, the processor asserts FAIL and then stops executing. 0 = self test failed 1 = self test passed TCK I I S(L) O R(Q) HQ) P(Q) TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. TDO does not float during ONCE mode. TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan feature, connect a pulldown resistor between this pin and VSS. If TAP is not used, this pin must be connected to VSS; however, no resistor is required. See Section 4.3, "Connection Recommendations" on page 40. TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. POWER pins intended for external connection to a VCC board plane. PLL POWER is a separate VCC supply pin for the phase lock loop clock generator. It is intended for external connection to the VCC board plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. 5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O buffers. This signal should be connected to +5 V for use with inputs which exceed 3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V. GROUND pins intended for external connection to a VSS board plane. NO CONNECT pins. Do not make any system connections to these pins.
STEST
I S(L)
FAIL
O R(0) H(Q) P(1)
TDI
TDO
TRST
I A(L)
TMS VCC VCCPLL
I S(L) -
-
VCC5 VSS NC
- - -
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 5.
Pin Description -- Interrupt Unit Signals
NAME TYPE DESCRIPTION EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0 pins can be configured in three modes: Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs can be programmed to be level (low) or edge (falling) sensitive. XINT7:0 I A(E/L) Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins are level sensitive in this mode. Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act as the five most significant bits of a vectored source. The least significant bits of the vectored source are set to 0102 internally. Unused external interrupt pins should be connected to VCC. NMI I A(E) NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is unused, it should be connected to VCC.
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21
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.2
Figure 3.
80960Jx 132-Lead PGA Pinout
132-Lead Pin Grid Array Bottom View - Pins Facing Up
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P AD25 N AD27 M AD30 L BE2 K VCC J VCC H VCC G VCC F VCC E VCC D VCC C LOCK/ HOLDA BLAST ONCE B W/R A ADS WIDTH/ ALE HLTD1 NC NC VCC VCC VCC VCC NMI XINT7 XINT5 XINT2 TMS D/C WIDTH/ TDO HLTD0 NC VSS VSS VSS VSS XINT6 XINT4 XINT3 TCK NC A3 A2 FAIL VCC5 NC HOLD XINT1 XINT0 TRST STEST NC VSS DT/R TDI VSS VCC VSS DEN RESET VSS VCC VSS BSTAT RDYRCV VSS VCC VSS ALE NC VSS VCC VSS BE0 VCCPLL VSS CLKIN VSS BE1 NC VSS VCC VSS AD31 AD2 VSS VCC BE3 AD28 AD5 AD1 VCC AD29 NC AD23 AD21 AD17 AD16 AD15 AD14 AD12 AD9 AD8 AD4 AD0 AD26 AD24 AD20 VSS VSS VSS VSS VSS VSS VSS AD10 AD7 AD3 AD22 AD19 AD18 VCC VCC VCC VCC VCC VCC VCC AD13 AD11 AD6
P
N M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 4.
132-Lead Pin Grid Array Top View - Pins Facing Down
14 13 12 11 10 9 8 7 6 5 4 3 2 1
P AD6 N AD3 M AD0 L VCC K VCC J VCC H CLKIN G VCC F VCC E VCC D VCC C NC B NC A TMS XINT2 XINT5 XINT7 NMI VCC VCC VCC VCC NC NC ALE WIDTH/ HLTD1 ADS TCK XINT3 XINT4 XINT6 VSS VSS VSS VSS NC TDO WIDTH/ HLTD0 D/C W/R STEST TRST XINT0 XINT1 HOLD NC VCC5 FAIL A2 A3 BLAST HOLDA LOCK/ ONCE VSS TDI DT/R VSS VCC VSS RESET DEN VSS VCC VSS RDYRCV VSS NC VSS VCCPLL VSS NC VSS AD2 AD31 VSS VCC AD1 AD5 AD28 BE3 BE2 AD4 AD8 AD9 AD12 AD14 AD15 AD16 AD17 AD21 AD23 NC AD29 AD30 AD7 AD10 VSS VSS VSS VSS VSS VSS VSS AD20 AD24 AD26 AD27 AD11 AD13 VCC VCC VCC VCC VCC VCC VCC AD18 AD19 AD22 AD25
P
N M
L
K
J
i
11 10
A80960Jx
M
BE1 BE0 ALE
VSS VSS VSS
VCC H VCC G VCC F VCC E
(c) 19xx
XXXXXXXX SS
BSTAT VSS
D
C
B
A
14
13
12
9
8
7
6
5
4
3
2
1
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 6.
132-Lead PGA Pinout -- In Signal Order
Signal A2 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 Pin C5 C4 M14 L13 K12 N14 M13 L12 P14 N13 M12 M11 N12 P13 M10 P12 M9 M8 M7 M6 P4 P3 N4 M5 P2 M4 N3 P1 N2 N1 L3 M2 M1 Signal AD31 ADS ALE ALE BE0 BE1 BE2 BE3 BLAST BSTAT CLKIN D/C DEN DT/R FAIL HOLD HOLDA LOCK/ONCE NC NC NC NC NC NC NC NC NC NMI RDYRCV RESET STEST TCK TDI Pin K3 A1 G3 A3 H3 J3 L1 L2 C3 F3 H14 B2 E3 D3 C6 C9 C2 C1 A4 A5 B5 B14 C8 C14 G12 J12 M3 A10 F12 E12 C13 B13 D12 Signal TDO TMS TRST VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPLL VCC5 VSS VSS VSS Pin B4 A14 C12 A6 A7 A8 A9 D1 D14 E1 E14 F1 F14 G1 G14 H1 J1 J14 K1 K14 L14 P5 P6 P7 P8 P9 P10 P11 H12 C7 B6 B7 B8 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R WIDTH/HLTD0 WIDTH/HLTD1 XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 Pin B9 D2 D13 E2 E13 F2 F13 G2 G13 H2 H13 J2 J13 K2 K13 N5 N6 N7 N8 N9 N10 N11 B1 B3 A2 C11 C10 A13 B12 B11 A12 B10 A11
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 7.
132-Lead PGA Pinout -- In Pin Order
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 Signal ADS WIDTH/HLTD1 ALE NC NC VCC VCC VCC VCC NMI XINT7 XINT5 XINT2 TMS W/R D/C WIDTH/HLTD0 TDO NC VSS VSS VSS VSS XINT6 XINT4 XINT3 TCK NC LOCK/ONCE HOLDA BLAST A3 A2 Pin C6 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D12 D13 D14 E1 E2 E3 E12 E13 E14 F1 F2 F3 F12 F13 F14 G1 G2 G3 G12 G13 G14 Signal FAIL VCC5 NC HOLD XINT1 XINT0 TRST STEST NC VCC VSS DT/R TDI VSS VCC VCC VSS DEN RESET VSS VCC VCC VSS BSTAT RDYRCV VSS VCC VCC VSS ALE NC VSS VCC Pin H1 H2 H3 H12 H13 H14 J1 J2 J3 J12 J13 J14 K1 K2 K3 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 Signal VCC VSS BE0 VCCPLL VSS CLKIN VCC VSS BE1 NC VSS VCC VCC VSS AD31 AD2 VSS VCC BE2 BE3 AD28 AD5 AD1 VCC AD30 AD29 NC AD23 AD21 AD17 AD16 AD15 AD14 Pin M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Signal AD12 AD9 AD8 AD4 AD0 AD27 AD26 AD24 AD20 VSS VSS VSS VSS VSS VSS VSS AD10 AD7 AD3 AD25 AD22 AD19 AD18 VCC VCC VCC VCC VCC VCC VCC AD13 AD11 AD6
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.3
Figure 5.
80960Jx 132-Lead PQFP Pinout
132-Lead PQFP - Top View
AD4 V CC (I/O) VSS (I/O) AD3 AD2 AD1 AD0 VCC (I/O) VSS (I/O) VCC (Core) VSS (Core) V CC (Core) VSS (Core) CLKIN VSS (CLK) VCCPLL VCC (CLK) NC NC VCC (Core) VSS (Core) RESET NC NC STEST VCC (I/O) TDI VSS(I/O) RDYRCV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
AD8 AD7 AD6 AD5 AD9 VCC (I/O) VSS (I/O) AD10 AD11 VCC (I/O) VSS (I/O) VCC (Core) VSS (Core) AD12 AD13 AD14 AD15 VCC (I/O) VSS (I/O) AD16 AD17 AD18 AD19 VCC (I/O) VSS (I/O) AD20 AD21 AD22 AD23 VCC (Core) VSS (Core) VCC (I/O) VSS (I/O) AD24 AD25 AD26 NC
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
TRST TCK TMS HOLD XINT0 XINT1 XINT2 XINT3 VCC (I/O) VSS (I/O) XINT4 XINT5 XINT6 XINT7 NMI VCC (Core) VSS (Core) NC NC VCC5 NC NC FAIL ALE TDO VCC (I/O) VSS(I/O) WIDTH/HLTD1 VCC(Core) VSS (Core) WIDTH/HLTD0 A2 A3
i960
(R)
i
BLAST
NG80960Jx
XXXXXXXX SS
M
(c) 19xx
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 AD27 VCC (I/O) VSS (I/O) AD28 AD29 AD30 AD31 VCC (Core) VSS (Core) VCC (I/O) VSS (I/O) BE3 BE2 BE1 BE0 BSTAT LOCK/ONCE VCC (I/O) VSS (I/O) VCC (Core) VSS (Core) ALE HOLDA DEN DT/R VCC (I/O) VSS (I/O) VCC (Core) VSS (Core) W/R ADS D/C
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 8.
132-Lead PQFP Pinout -- In Signal Order
Signal AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ALE Pin 60 61 62 63 66 68 69 70 75 76 77 78 81 82 83 84 87 88 89 90 95 96 99 100 101 102 103 104 107 108 109 110 45 Signal ALE ADS A3 A2 BE3 BE2 BE1 BE0 WIDTH/HLTD1 WIDTH/HLTD0 D/C W/R DT/R DEN BLAST RDYRCV LOCK/ONCE HOLD HOLDA BSTAT CLKIN RESET STEST FAIL TCK TDI TDO TRST TMS VCC (CLK) VCC (Core) VCC (Core) VCC (Core) Pin 24 36 33 32 55 54 53 52 28 31 35 37 42 43 34 132 50 4 44 51 117 125 128 23 2 130 25 1 3 120 16 29 39 Signal VCC (Core) VCC (Core) VCC (Core) VCC (Core) VCC (Core) VCC (Core) VCC (Core) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCC (I/O) VCCPLL VCC5 VSS (CLK) VSS (Core) VSS (Core) VSS (Core) VSS (Core) VSS (Core) VSS (Core) VSS (Core) VSS (Core) VSS (Core) Pin 47 59 74 92 113 115 123 9 26 41 49 57 65 72 80 86 94 98 105 111 129 119 20 118 17 30 38 46 58 73 91 114 116 Signal VSS (Core) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) VSS (I/O) NC NC NC NC NC NC NC NC NC XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 NMI Pin 124 10 27 40 48 56 64 71 79 85 93 97 106 112 131 18 19 21 22 67 121 122 126 127 14 13 12 11 8 7 6 5 15
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 9.
132-Lead PQFP Pinout -- In Pin Order
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal TRST TCK TMS HOLD XINT0 XINT1 XINT2 XINT3 VCC (I/O) VSS (I/O) XINT4 XINT5 XINT6 XINT7 NMI VCC (Core) VSS (Core) NC NC VCC5 NC NC FAIL ALE TDO VCC (I/O) VSS (I/O) WIDTH/HLTD1 VCC (Core) VSS (Core) WIDTH/HLTD0 A2 A3 Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal BLAST D/C ADS W/R VSS (Core) VCC (Core) VSS (I/O) VCC (I/O) DT/R DEN HOLDA ALE VSS (Core) VCC (Core) VSS (I/O) VCC (I/O) LOCK/ONCE BSTAT BE0 BE1 BE2 BE3 VSS (I/O) VCC (I/O) VSS (Core) VCC (Core) AD31 AD30 AD29 AD28 VSS (I/O) VCC (I/O) AD27 Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal NC AD26 AD25 AD24 VSS (I/O) VCC (I/O) VSS (Core) VCC (Core) AD23 AD22 AD21 AD20 VSS (I/O) VCC (I/O) AD19 AD18 AD17 AD16 VSS (I/O) VCC (I/O) AD15 AD14 AD13 AD12 VSS (Core) VCC (Core) VSS (I/O) VCC (I/O) AD11 AD10 VSS (I/O) VCC (I/O) AD9 Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal AD8 AD7 AD6 AD5 AD4 VCC (I/O) VSS (I/O) AD3 AD2 AD1 AD0 VCC (I/O) VSS (I/O) VCC (Core) VSS (Core) VCC (Core) VSS (Core) CLKIN VSS (CLK) VCCPLL VCC (CLK) NC NC VCC (Core) VSS (Core) RESET NC NC STEST VCC (I/O) TDI VSS (I/O) RDYRCV
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.4
Figure 6.
80960Jx 196-Ball MPBGA Pinout
196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A NC B VCC C NC D NC E NC F NC G NC H BE1 J VCC K ALE L HOLDA M DT/R N W/R P NC ADS BLAST VCC WIDTH0 WIDTH1 FAIL NC NC NMI XINT7 XINT5 VCC NC D/C NC NC A2 VCC TDO NC XINT4 NC XINT6 XINT1 XINT3 HOLD VCC NC NC A3 VCC ALE VCC5 VCC XINT2 XINT0 TMS TRST TCK LOCK/ ONCE DEN VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC VCC STEST BE0 BSTAT VSS VSS VSS VSS VSS VSS VSS VSS TDI NC RESET BE2 BE3 VSS VSS VSS VSS VSS VSS VSS VSS NC VCC NC NC VCC VSS VSS VSS VSS VSS VSS VSS VSS NC CLKIN NC NC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCCPLL NC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC NC NC VSS VSS VSS VSS VSS VSS VSS AD3 AD5 AD0 AD1 AD31 NC AD26 AD25 AD24 AD21 AD19 AD16 VCC VCC AD11 AD6 AD2 AD30 AD27 AD29 VCC AD23 AD20 AD17 AD14 AD12 AD10 AD9 AD7 AD4 AD28 VCC NC VCC AD22 VCC AD18 VCC AD15 AD13 VCC AD8 NC
A
B
C
D
E
F
G
H
J
K
L NC RDYRCV M N
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
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80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 7.
196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A NC B AD4 C AD2 D AD1 E VCC F VCCPLL VCC G NC H NC J RESET K STEST L RDYRCV NC M TCK N HOLD XINT3 XINT1 XINT6 P NC VCC XINT5 XINT7 NMI NC NC FAIL WIDTH1 WIDTH0 VCC BLAST ADS NC NC XINT4 NC TDO VCC A2 NC NC D/C W/R TRST TMS XINT0 XINT2 VCC VCC5 ALE VCC A3 NC NC VCC DT/R NC VSS VSS VSS VSS VSS VSS VSS VSS VCC DEN HOLDA VCC NC VSS VSS VSS VSS VSS VSS VSS VSS VCC LOCK/ ONCE ALE NC TDI VSS VSS VSS VSS VSS VSS VSS VSS BSTAT BE0 VCC VCC NC VSS VSS VSS VSS VSS VSS VSS VSS BE3 BE2 BE1 CLKIN NC VSS VSS VSS VSS VSS VSS VSS VSS VCC NC NC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC NC NC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC NC NC AD0 AD5 AD3 VSS VSS VSS VSS VSS VSS VSS NC NC NC AD6 AD11 VCC VCC AD16 AD19 AD21 AD24 AD25 AD26 NC AD31 NC AD7 AD9 AD10 AD12 AD14 AD17 AD20 AD23 VCC AD29 AD27 AD30 VCC AD8 VCC AD13 AD15 VCC AD18 VCC AD22 VCC NC VCC AD28 NC
A
B
C
D
E
F
G
H
J
K
L
M N
P
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 10.
196-Ball MPBGA Pinout -- In Signal Order (Sheet 1 of 2)
Signal A2 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADS ALE ALE Pin N5 M5 D13 D14 C14 D11 B14 D12 C13 B13 A13 B12 B11 C12 B10 A11 B9 A10 C9 B8 A8 C8 B7 C7 A6 B6 C6 C5 C4 B3 A2 B4 B2 C2 P2 K1 M7 Signal BE0 BE1 BE2 BE3 BLAST BSTAT CLKIN DEN D/C DT/R FAIL HOLD HOLDA LOCK/ONCE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin J2 H1 H2 H3 P3 J3 G13 L2 N2 M1 P7 N14 L1 K2 A1 A4 A14 C1 C3 D1 D2 D3 E1 E2 F1 F2 G1 G2 G12 G14 H12 H14 J13 K12 L12 L13 M3 Signal NC NC NC NC NC NC NC NC NC NMI RDYRCV RESET STEST TCK TDI TDO TMS TRST VCC5 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin M4 N3 N4 N8 N10 P1 P8 P9 P14 P10 L14 J14 K14 M14 J12 N7 M12 M13 M8 A3 A5 A7 A9 A12 B1 B5 C10 C11 E3 E12 E13 E14 F3 F12 F13 G3 H13 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin J1 K3 K13 L3 M2 M6 M9 N6 P4 P13 F14 D4 D5 D6 D7 D8 D9 D10 E4 E5 E6 E7 E8 E9 E10 E11 F4 F5 F6 F7 F8 F9 F10 F11 G4 G5 G6
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 10.
196-Ball MPBGA Pinout -- In Signal Order (Sheet 2 of 2)
Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin G7 G8 G9 G10 G11 H4 H5 H6 H7 H8 H9 H10 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin H11 J4 J5 J6 J7 J8 J9 J10 J11 K4 K5 K6 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin K7 K8 K9 K10 K11 L5 L6 L7 L8 L9 L10 L4 Signal VSS WIDTH0 WIDTH1 W/R XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 Pin L11 P5 P6 N1 M11 N12 M10 N13 N9 P12 N11 P11
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 11.
196-Ball MPBGA Pinout -- In Pin Order (Sheet 1 of 2)
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Signal NC AD28 VCC NC VCC AD22 VCC AD18 VCC AD15 AD13 VCC AD8 NC VCC AD30 AD27 AD29 VCC AD23 AD20 AD17 AD14 AD12 AD10 AD9 AD7 AD4 NC AD31 NC AD26 AD25 AD24 AD21 AD19 AD16 VCC Pin C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 Signal VCC AD11 AD6 AD2 NC NC NC VSS VSS VSS VSS VSS VSS VSS AD3 AD5 AD0 AD1 NC NC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC NC NC VCC VSS VSS VSS Pin F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 Signal VSS VSS VSS VSS VSS VCC VCC VCCPLL NC NC VCC VSS VSS VSS VSS VSS VSS VSS VSS NC CLKIN NC BE1 BE2 BE3 VSS VSS VSS VSS VSS VSS VSS VSS NC VCC NC VCC BE0 Pin J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 Signal BSTAT VSS VSS VSS VSS VSS VSS VSS VSS TDI NC RESET ALE LOCK/ONCE VCC VSS VSS VSS VSS VSS VSS VSS VSS NC VCC STEST HOLDA DEN VCC VSS VSS VSS VSS VSS VSS VSS VSS NC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 11.
196-Ball MPBGA Pinout -- In Pin Order (Sheet 2 of 2)
Pin L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 Signal NC RDYRCV DT/R VCC NC NC A3 VCC ALE VCC5 VCC Pin M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 Signal XINT2 XINT0 TMS TRST TCK W/R D/C NC NC A2 VCC Pin N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 Signal TDO NC XINT4 NC XINT6 XINT1 XINT3 HOLD NC ADS BLAST Pin P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Signal VCC WIDTH0 WIDTH1 FAIL NC NC NMI XINT7 XINT5 VCC NC
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
3.2
Package Thermal Specifications
The 80960Jx is specified for operation when TC (case temperature) is within the range of 0C to 100C for PGA, MPBGA and PQFP packages. An extended temperature device is also available in a PQFP package with TC -40C to 100C. Case temperature may be measured in any environment to determine whether the 80960Jx is within its specified operating range. The case temperature should be measured at the center of the top surface, opposite the pins. CA is the thermal resistance from case to ambient. Use the following equation to calculate TA, the maximum ambient temperature to conform to a particular case temperature:
TA = TC - P (CA)
Junction temperature (TJ) is commonly used in reliability calculations. TJ can be calculated from JC (thermal resistance from junction to case) using the following equation:
TJ = TC + P (JC)
Similarly, if TA is known, the corresponding case temperature (TC) can be calculated as follows:
TC = TA + P (CA)
Compute P by multiplying ICC from Table 22 and VCC. Values for JC and CA are given in Table 12 for the PGA package, Table 13 for the MPBGA package, and Table 14 for the PQFP package. For high speed operation, the processor's JA may be significantly reduced by adding a heatsink and/or by increasing airflow. Tables 15, 16, and 17 show the maximum ambient temperature (TA) permitted without exceeding TC for the PGA, MPBGA, and PQFP packages. The values are based on typical ICC and VCC of +3.3 V, with a TCASE of +100C.
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Table 12.
132-Lead PGA Package Thermal Characteristics
Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter JC (Junction-to-Case) CA (Case-to-Ambient) (No Heatsink) CA (Case-to-Ambient) (Omnidirectional Heatsink) CA (Case-to-Ambient) (Unidirectional Heatsink) JA JC J-PIN J-CAP 0 (0) 0.7 25 15 16 200 (1.01) 0.7 19 9 8 CA 400 (2.03) 0.7 14 6 6 600 (3.04) 0.7 12 5 5 800 (4.06) 0.7 11 4 4 1000 (5.08) 0.7 10 4 4
NOTES: 1. This table applies to a PGA device plugged into a socket or soldered directly into a board. 2. JA = JC + CA 3. J-CAP = 5.6C/W (approximate) (no heatsink) 4. J-PIN = 6.4C/W (inner pins) (approximate) (no heatsink) 5. J-PIN = 6.2C/W (outer pins) (approximate) (no heatsink) 6. J-CAP = 3C/W (approximate) (with heatsink) 7. J-PIN = 3.3C/W (inner pins) (approximate) (with heatsink) 8. J-PIN = 3.3C/W (outer pins) (approximate) (with heatsink)
Table 13.
196-Ball MPBGA Package Thermal Characteristics
Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter JC (Junction-to-Case) CA (Case-to-Ambient) (No Heatsink) CA (Case-to-Ambient) (Omnidirectional Heatsink) CA (Case-to-Ambient) (Unidirectional Heatsink) 0 (0) TBD TBD TBD TBD 200 (1.01) TBD TBD TBD TBD 400 (2.03) TBD TBD TBD TBD 600 (3.04) TBD TBD TBD TBD 800 (4.06) TBD TBD TBD TBD 1000 (5.08) TBD TBD TBD TBD
TBD
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 14.
132-Lead PQFP Package Thermal Characteristics
Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter JC (Junction-to-Case) CA (Case-to-Ambient -No Heatsink) 0 (0) 4.1 23 50 (0.25) 4.3 19 JA 100 (0.50) 4.3 18 CA JC 200 (1.01) 4.3 16 400 (2.03) 4.3 14 600 (3.04) 4.7 11 800 (4.06) 4.9 9
JB
JL
NOTES: 1. This table applies to a PQFP device soldered directly into board. 2. JA = JC + CA 3. JL = 13C/W (approx.) 4. JB = 13.5C/W (approx.)
Table 15.
Maximum TA at Various Airflows in C (80960JT)
Airflow-ft/min (m/sec) fCLKIN (MHz) PQFP Package TA without Heatsink TA without Heatsink PGA Package TA with Omnidirectional Heatsink1 TA with Unidirectional Heatsink2 MPBGA Package TA without Heatsink 33 25 33 25 33 25 33 25 33 25 0 (0) 62 71 58 68 75 81 73 79 TBD TBD 200 (1.01) 73 79 68 75 85 88 86 90 TBD TBD 400 (2.03) 76 82 76 82 90 92 90 92 TBD TBD 600 (3.04) 81 86 80 84 92 94 92 94 TBD TBD 800 (4.06) 85 88 81 86 93 95 93 95 TBD TBD 1000 (5.07) 88 91 83 87 93 95 93 95 TBD TBD
NOTES: 1. 0.248" high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
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Table 16.
Maximum TA at Various Airflows in C (80960JD)
Airflow-ft/min (m/sec) fCLKIN (MHz) TA without Heatsink 33 25 20 16.67 33 25 20 16.67 33 25 20 16.67 33 25 20 16.67 25 20 16.67 0 (0) 61 70 75 79 58 68 73 78 75 81 84 87 73 79 82 86 TBD TBD TBD 200 (1.01) 73 79 82 86 68 75 79 83 85 88 90 92 86 90 91 93 TBD TBD TBD 400 (2.03) 76 82 85 87 76 82 85 87 90 92 93 95 90 92 93 95 TBD TBD TBD 600 (3.04) 81 86 88 90 80 84 87 89 92 94 95 96 92 94 95 96 TBD TBD TBD 800 (4.06) 85 88 90 92 81 86 88 90 93 95 96 96 93 95 96 96 TBD TBD TBD 1000 (5.07) 86 90 91 93 83 87 89 91 93 95 96 96 93 96 96 96 TBD TBD TBD
PQFP Package
TA without Heatsink
PGA Package
TA with Omnidirectional Heatsink1
TA with Unidirectional Heatsink2
MPBGA Package
TA without Heatsink
NOTES: 1. 0.248" high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 17.
Maximum TA at Various Airflows in C (80960JA/JF)
Airflow-ft/min (m/sec) fCLKIN (MHz) For NG80960JA/JF PQFP Package TA without Heatsink For TG80960JA-25 TA without Heatsink TA without Heatsink 33 25 16 25 33 25 16 33 25 16 33 25 16 33 25 16 0 (0) 79 84 89 84 78 83 88 87 90 93 86 89 92 TBD TBD TBD 200 (1.01) 86 89 92 89 83 87 91 92 94 96 93 94 96 TBD TBD TBD 400 (2.03) 87 90 93 90 87 90 93 95 96 97 95 96 97 TBD TBD TBD 600 (3.04) 90 92 95 92 89 92 94 96 97 98 96 97 98 TBD TBD TBD 800 (4.06) 92 94 96 94 90 92 95 96 97 98 96 97 98 TBD TBD TBD 1000 (5.07) 93 94 96 94 91 93 95 96 97 98 96 97 98 TBD TBD TBD
PGA Package
TA with Omnidirectional Heatsink1 TA with Unidirectional Heatsink2 TA without Heatsink
MPBGA Package
NOTES: 1. 0.248" high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
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80960JA/JF/JD/JT 3.3 V Microprocessor
3.3
Thermal Management Accessories
The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an endorsement or a warranty of the performance of any of the listed products and/or companies.
3.3.1
Heatsinks
1. Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75234-8993 (972) 243-4321 2. Wakefield Engineering 60 Audubon Road Wakefield, MA 01880 (617) 245-5900 3. Aavid Thermal Technologies, Inc. One Kool Path Laconia, NH 03247-0400 (603) 528-3400
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80960JA/JF/JD/JT 3.3 V Microprocessor
4.0
4.1
Warning:
Electrical Specifications
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. This document contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications within this data sheet are subject to change without notice. Verify with your local Intel sales office that you have the latest data sheet before finalizing a design. Absolute Maximum Ratings
Parameter Storage Temperature Case Temperature Under Bias Supply Voltage wrt. VSS Voltage on VCC5 wrt. VSS Voltage on Other Pins wrt. VSS -65 C to +150 C -65oC to +110oC -0.5 V to + 4.6 V -0.5 V to + 6.5 V -0.5 V to VCC + 0.5 V
o o
Note:
Table 18.
Maximum Rating
4.2
Operating Conditions
Table 19 indicates the operating conditions for the 80960Jx.
Table 19.
80960Jx Operating Conditions
Symbol VCC VCC5 Supply Voltage Input Protection Bias Input Clock Frequency 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 Operating Case Temperature PGA, MPBGA, and PQFP Extended temp PQFP (TG80960JA-25) 15 15 12 12 12 12 12 12 12 0 -40 33.3 25 33.3 25 20 16.67 33.3 25 16 100 100 Parameter Min 3.15 3.15 Max 3.45 5.5 Units V V (1) Notes
fCLKIN
MHz
TC
C
NOTE: 1. See Section 4.4, "VCC5 Pin Requirements (VDIFF)" on page 40.
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80960JA/JF/JD/JT 3.3 V Microprocessor
4.3
Connection Recommendations
For clean on-chip power distribution, VCC and VSS pins separately feed the device's functional units. Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board, every VCC pin should connect to a power plane and every VSS pin should connect to a ground plane. Place liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges. Pay special attention to the Test Reset (TRST) pin. It is essential that the JTAG Boundary Scan Test Access Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG Boundary Scan function will be used, connect a pulldown resistor between the TRST pin and VSS. If the JTAG Boundary Scan function will not be used (even for board-level testing), connect the TRST pin to VSS. Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used. Note: Pins identified as NC must not be connected in the system.
4.4
VCC5 Pin Requirements (VDIFF)
In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5 pin directly to the 3.3 V VCC plane. In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation, and prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and its 3.3 V VCC pins must not exceed 2.25 V. If this requirement is not met, current flow through the pin may exceed the value at which the processor is damaged. Instances when the voltage can exceed 2.25 V is during power up or power down, where one source reaches its level faster than the other, briefly causing an excess voltage differential. Another instance is during steady-state operation, where the differential voltage of the regulator (provided a regulator is used) cannot be maintained within 2.25 V. Two methods are possible to prevent this from happening:
* Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V, or, * As shown in Figure 8, place a 100 resistor in series with the VCC5 pin to limit the current
through VCC5. Figure 8. VCC5 Current-Limiting Resistor
+5 V (0.25 V)
VCC5 Pin
100 (5%, 0.5 W)
If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and reliable method for limiting current. The resistor can also prevent damage in the case of a power failure, where the 5 V supply remains on and the 3.3 V supply goes to zero. Table 20. VDIFF Parameters
Symbol VDIFF Parameter VCC5-VCC Difference Min Max 2.25 Units V Notes VCC5 input should not exceed VCC by more than 2.25 V during power-up and power-down, or during steady-state operation.
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4.5
VCCPLL Pin Requirements
To reduce clock skew on the i960 80960Jx processor, the VCCPLL pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise induced clock jitter and its effects on timing relationships in system designs. The 4.7 F capacitor must be low ESR solid tantalum; the 0.01 F capacitor must be of the type X7R and the node connecting VCCPLL must be as short as possible.
Figure 9.
VCCPLL Lowpass Filter
100 (80960JA/JF/JD) 10 (80960JT)
VCC (Board Plane)
+ 4.7 F 0.01 F
VCCPLL (On 80960Jx)
F_CA078A
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80960JA/JF/JD/JT 3.3 V Microprocessor
4.6
Table 21.
DC Specifications
80960Jx DC Characteristics
Symbol VIL VIH VOL VOH VOLP CIN Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Ground Bounce Input Capacitance PGA PQFP MPBGA I/O or Output Capacitance PGA PQFP MPBGA CLKIN Capacitance PGA PQFP MPBGA 2.4 VCC - 0.2 <0.8 15 15 15 15 15 15 15 15 15 Min -0.3 2.0 Typ Max 0.8 VCC5 + 0.3 0.4 0.2 Units V V V V V V IOL = 3 mA IOL = 100 A IOH = -1 mA IOH = -200 A (1,2) Notes
pF
fCLKIN = fMIN (2)
COUT
pF
fCLKIN = fMIN (2)
CCLK
pF
fCLKIN = fMIN (2)
NOTES: 1. Typical is measured with VCC = 3.3 V and temperature = 25 C. 2. Not tested.
Table 22.
80960Jx ICC Characteristics (Sheet 1 of 2)
Symbol ILI1 ILI2 ILO Rpu Parameter Input Leakage Current for each pin except TCK, TDI, TRST and TMS Input Leakage Current for TCK, TDI, TRST and TMS Output Leakage Current Internal Pull-UP Resistance for ONCE, TMS, TDI and TRST 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 20 -140 Typ Max 1 -250 1 30 600 450 580 447 367 310 320 260 194 Units A A A k (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) Notes 0 VIN VCC VIN = 0.45V (1) 0.4 VOUT VCC
ICC Active (Power Supply)
mA
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 22.
80960Jx ICC Characteristics (Sheet 2 of 2)
Symbol Parameter 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 Reset mode 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 ICC Test (Power modes) Halt mode 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 ONCE mode 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 50 40 50 40 34 34 31 26 21 10 450 400 475 425 345 300 250 200 150 mA (5) (5) (5) (5) (5) (5) (5) (5) (5) (5) (6) (6) (6) (6) (6) (6) (6) (6) (6) (5) (5) (5) (5) (5) (5) (5) (5) Typ 500 380 510 390 320 260 271 215 152 Max Units Notes (2,4) (2,4) (2,4) (2,4) (2,4) (2,4) (2,4) (2,4) (2,4)
ICC Active (Thermal)
mA
ICC5 Current on the VCC5 Pin
200
A
NOTES: 1. These pins have internal pullup devices. Typical leakage current is not tested. 2. Measured with device operating and outputs loaded to the test condition in Figure 10 "AC Test Load" on page 47. 3. ICC Active (Power Supply) value is provided for selecting your system's power supply. It is measured using one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested. 4. ICC Active (Thermal) value is provided for your system's thermal management. Typical ICC is measured with VCC =3.3 V and temperature = 25C. This parameter is characterized but not tested. 5. ICC Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode, Halt mode or ONCE mode with VCC = 3.45 V. 6. ICC5 is tested at VCC = 3.3 V, VCC5 = 5.25 V.
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80960JA/JF/JD/JT 3.3 V Microprocessor
4.7
AC Specifications
The 80960Jx AC timings are based upon device characterization.
Table 23.
80960Jx AC Characteristics (Sheet 1 of 3)
Symbol Parameter Min INPUT CLOCK TIMINGS CLKIN Frequency 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 CLKIN Period 80960JT-100 80960JT-75 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA/JF-16 CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time 8 8 4 4 SYNCHRONOUS OUTPUT TIMINGS Output Valid Delay, Except ALE/ALE Inactive and DT/R for 3.3 V input signals Same as above, but for 5.5 V input signals Output Valid Delay, DT/R TOV2 80960JT 80960JD 80960JA/JF Output Float Delay 0.5TC + 7 0.5TC + 7 0.5TC + 4 2.5 0.5TC + 9 0.5TC + 9 0.5TC + 18 13.5 ns 2.5 2.5 13.5 ns 16.5 (3) 30 40 30 40 50 60 30 40 62.5 66.7 66.7 83.3 83.3 83.3 83.3 83.3 83.3 83.3 15 15 12 12 12 12 12 12 12 33.3 25 33.3 25 20 16.67 33.3 25 16 Max Unit Notes
TF
MHz
TC
ns
TCS TCH TCL TCR TCF
250
ps ns ns ns ns
(1, 2) Measured at 1.5 V (1) Measured at 1.5 V (1) 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1)
TOV1
TOF NOTE:
ns
(4)
See Table 24 on page 47 for note definitions for this table.
44
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 23.
80960Jx AC Characteristics (Sheet 2 of 3)
Symbol Parameter Min Max Unit Notes
SYNCHRONOUS INPUT TIMINGS Input Setup to CLKIN -- AD31:0, NMI, XINT7:0 TIS1 80960JT 80960JD 80960JA/JF Input Hold from CLKIN -- AD31:0, NMI, XINT7:0 TIH1 80960JT 80960JD 80960JA/JF Input Setup to CLKIN -- RDYRCV and HOLD TIS2 80960JT 80960JD 80960JA/JF Input Hold from CLKIN -- RDYRCV and HOLD Input Setup to CLKIN -- RESET TIS3 80960JT 80960JD 80960JA/JF Input Hold from CLKIN -- RESET TIH3 80960JT 80960JD 80960JA/JF Input Setup to RESET -- ONCE, STEST TIS4 80960JT 80960JD 80960JA/JF Input Hold from RESET -- ONCE, STEST TIH4 80960JT 80960JD 80960JA/JF 2 2 1 RELATIVE OUTPUT TIMINGS Address Valid to ALE/ALE Inactive TLX TLXL TLXA TDXD For 3.3 V Data Input Signals For 5.0 V Data Input Signals ALE/ALE Width Address Hold from ALE/ALE Inactive DT/R Valid to DEN Active BOUNDARY SCAN TEST SIGNAL TIMINGS TBSF TBSCH TBSCL TBSCR TBSCF NOTE:
See Table 24 on page 47 for note definitions for this table.
6 6 9
ns
(5)
1.5 1.5 1.0
ns
(5)
6.5 6.5 10.0 1
ns
(6)
TIH2
ns
(6)
7 7 8 2 2 1 7 7 8
ns
(7)
ns
(7)
ns
(8)
ns
(8)
0.5TC - 5 0.5TC - 8 0.5TC - 7
ns
(9)
ns
Equal Loading (9)
TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time 15 15
0.5TF
MHz ns ns Measured at 1.5 V (1) Measured at 1.5 V (1) 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1)
5 5
ns ns
Advance Information Datasheet
45
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 23.
80960Jx AC Characteristics (Sheet 3 of 3)
Symbol TBSIS1 TBSIH1 TBSOV1 TBSOF1 TBSOV2 TBSOF2 TBSIS2 TBSIH2 NOTE:
See Table 24 on page 47 for note definitions for this table.
Parameter Input Setup to TCK -- TDI, TMS Input Hold from TCK -- TDI, TMS TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay Input Setup to TCK -- All Inputs (Non-Test) Input Hold from TCK -- All Inputs (Non-Test)
Min 4 6 3 3 3 3 4 6
Max
Unit ns ns
Notes
30 30 30 30
ns ns ns ns ns ns
(1,10) (1,10) (1,10) (1,10)
46
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 24.
Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)
NOTES: 1. Not tested. 2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN frequency. 3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE timings, refer to Relative Output Timings in this table. 4. A float condition occurs when the output current becomes less than IOL. Float delay is not tested, but is designed to be no longer than the valid delay. 5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a minimum of two CLKIN periods to guarantee recognition. 6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor operation. 7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. 8. ONCE and STEST must be stable at the rising edge of RESET for proper operation. 9. Guaranteed by design. May not be 100% tested. 10.Relative to falling edge of TCK. 11.Worst-case TOV condition occurs on I/O pins when pins transition from a floating high input to driving a low output state. The Address/Data Bus pins encounter this condition between the last access of a read, and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at 50 pF loads.
4.7.1
AC Test Conditions and Derating Curves
The AC Specifications in Section 4.7, "AC Specifications" are tested with the 50 pF load indicated in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load capacitance.
Figure 10.
AC Test Load
Output Pin CL CL = 50 pF for all signals
Advance Information Datasheet
47
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 11.
Output Delay or Hold vs. Load Capacitance
AC Timings vs. Load Capacitance
nom + 7 nom + 6 nom + 5 Tov (ns) nom + 4 nom + 3 nom + 2 nom + 1 nom + 0 50
Rise and Fall times are identical.
Rising Falling
100 AD Bus Capacitive Load (pF)
150
Figure 12.
TLX vs. AD Bus Load Capacitance
AC Timings vs. Load Capacitance
nom + 7 nom + 6 nom + 5 Tlx (ns) nom + 4 nom + 3 nom + 2 nom + 1 nom + 0 50
Rise and Fall times are identical.
Rising Falling
100 AD Bus Capacitive Load (pF)
150
Note:
The TLX Derating curve applies only when an imbalance in the capacitive load occurs between the AD bus and ALE. The TLX derating is based on a 50 pF load on ALE. The derating applies to ALE and ALE.
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 13.
80960JA/JF ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs Frequency
350 300 250 200 150 100 50 0 12 15 18 21 24 27 30 33 CLKIN Frequency MHz
Figure 14.
80960JA/JF ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
300 Icc Active (Thermal) (mA)
ICC Active (Thermal) (mA) ICC Active (Thermal) vs. Frequency
250 200 150 100 50 0 12 15 18 21 24 27 30 33 CLKIN Frequency MHz
Advance Information Datasheet
Icc Active (Power Supply) (mA)
49
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 15.
80960JD ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs. Frequency
600 Icc Active (Power Supply) (mA) 500 400 300 200 100 0 12 15 18 21 24 27 30 33 CLKIN Frequency (MHz)
Figure 16.
80960JD ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
600 Icc Active (Thermal) (mA) 500 400 300 200 100 0 12 15 18 21 24 27 30 33 CLKIN Frequency (MHz)
50
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 17.
80960JT ICC Active (Power Supply) vs. Frequency
Icc Active (Power Supply) vs. Frequency
600 Icc Active (Power Supply) (mA) 500 400 300 200 100 0 15 18 21 24 27 30 33 CLKIN Frequency (MHz)
Figure 18.
80960JT ICC Active (Thermal) vs. Frequency
Icc Active (Thermal) vs. Frequency
1000 Icc Active (Thermal) (mA) 800 600 400 200 0 15 18 21 24 27 30 33 CLKIN Frequency (MHz)
Advance Information Datasheet
51
80960JA/JF/JD/JT 3.3 V Microprocessor
4.7.2
Figure 19.
AC Timing Waveforms
CLKIN Waveform
TCR
TCF
2.0V
1.5V
0.8V
TCH
TCL
TC
Figure 20.
TOV1 Output Delay Waveform
CLKIN
1.5V
1.5V
TOV1
AD31:0, ALE (active), ALE (active), ADS, A3:2, BE3:0, WIDTH/HLTD1:0, D/C, W/R, DEN, BLAST, LOCK, HOLDA, BSTAT, FAIL
1.5V
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 21.
TOF Output Float Waveform
CLKIN
1.5V
1.5V
TOF
AD31:0, ALE, ALE ADS, A3:2, BE3:0, WIDTH/HLTD1:0, D/C, W/R, DT/R, DEN, BLAST, LOCK
Figure 22.
TIS1 and TIH1 Input Setup and Hold Waveform
CLKIN
1.5V
1.5V
1.5V
TIH1 TIS1
AD31:0 NMI XINT7:0
1.5V
Valid
Figure 23.
TIS2 and TIH2 Input Setup and Hold Waveform
CLKIN
1.5V
1.5V
1.5V
TIH2 TIS2
HOLD, RDYRCV
1.5V
Valid
1.5V
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53
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 24.
TIS3 and TIH3 Input Setup and Hold Waveform
CLKIN
1.5V
1.5V
TIH3
TIS3
RESET
Figure 25.
TIS4 and TIH4 Input Setup and Hold Waveform
RESET
TIH4 TIS4
ONCE, STEST
Valid
54
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 26.
TLX, TLXL and TLXA Relative Timings Waveform
Ta Tw/Td
CLKIN
1.5V TLXL
1.5V
1.5V
ALE ALE
1.5V
Valid
1.5V
TLX
TLXA 1.5V
AD31:0
1.5V
Valid
Figure 27.
DT/R and DEN Timings Waveform
Ta Tw/Td
CLKIN
1.5V TOV2
1.5V
1.5V
DT/R
Valid
TDXD
DEN
TOV1
Advance Information Datasheet
55
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 28.
TCK Waveform
TBSCR
TBSCF
2.0V
1.5V
0.8V
TBSCH
TBSCL
Figure 29.
TBSIS1 and TBSIH1 Input Setup and Hold Waveforms
TCK
1.5V
TBSIS1
1.5V
TBSIH1
1.5V
TMS TDI
1.5V
Valid
1.5V
Figure 30.
TBSOV1 and TBSOF1 Output Delay and Output Float Waveform
TCK
1.5V
1.5V
1.5V
TBSOV1
TBSOF1
TDO
1.5V
Valid
56
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 31.
TBSOV2 and TBSOF2 Output Delay and Output Float Waveform
TCK
1.5V
1.5V
1.5V
TBSOV2
TBSOF2
Non-Test Outputs
1.5V
Valid
Figure 32.
TBSIS2 and TBSIH2 Input Setup and Hold Waveform
TCK
1.5V
1.5V TBSIH2
1.5V
TBSIS2
Non-Test Inputs
1.5V
Valid
1.5V
Advance Information Datasheet
57
80960JA/JF/JD/JT 3.3 V Microprocessor
5.0
Bus Functional Waveforms
Figure 33 through Figure 38 illustrate typical 80960Jx bus transactions. Figure 39 depicts the bus arbitration sequence. Figure 40 illustrates the processor reset sequence from the time power is applied to the device. Figure 41 illustrates the processor reset sequence when the processor is in operation. Figure 42 illustrates the processor ONCE sequence from the time power is applied to the device. Figure 44 and Figure 45 also show accesses on 32-bit buses. Table 27 through Table 29 summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to data alignment.
Figure 33.
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
Ta CLKIN Td Tr Ti Ti Ta Td Tr Ti Ti
AD31:0
ADDR
D In
Invalid
ADDR
DATA Out
ALE
ADS
A3:2
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF030A
58
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 34.
Burst Read and Write Transactions Without Wait States, 32-Bit Bus
TA CLKIN TD TD TR TA TD TD TD TD TR
AD31:0
ADDR
D In
D In
ADDR
DATA DATA DATA Out Out Out
DATA Out
ALE
ADS
A3:2
00 or 10
01 or 11
00
01
10
11
BE3:0
WIDTH1:0
10
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
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59
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 35.
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
TA CLKIN TW TW TD TW TD TW TD TW TD TR
AD31:0
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS
A3:2
00
01
10
11
BE3:0
WIDTH1:0
10
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF032A
60
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 36.
Burst Read and Write Transactions Without Wait States, 8-Bit Bus
TA CLKIN TD TD TR TA TD TD TD TD TR
AD31:0
ADDR
D In
D In
ADDR DATA DATA DATA
Out
Out
Out
DATA Out
ALE
ADS
A3:2
00,01,10 or 11
00,01,10 or 11
BE1/A1 BE0/A0
00 or 10
01 or 11
00
01
10
11
WIDTH1:0
00
00
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF033A
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61
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 37.
Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus
TA CLKIN TW TD TD TR TR TA TW TD TD TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
ALE
ADS
A3:2
00,01,10, or 11
00,01,10, or 11
BE1/A1
0
1
0
1
BE3/BHE BE0/BLE
WIDTH1:0
01
01
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
F_JF034A
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80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 38.
Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian
TA CLKIN TD TR TA TD TR TA TD TR TA TD TR
AD31:0
A
D In
A
D In
A
D In
A
D In
ALE
ADS
A3:2
00
00
01
10
BE3:0
1101
0011
0000
1110
WIDTH1:0
10
D/C
Valid
W/R
BLAST
DT/R
DEN
RDYRCV
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63
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 39.
HOLD/HOLDA Waveform For Bus Arbitration
TI or TR TH TH TI or TA
CLKIN
~
Outputs: AD31:0, ALE, ALE, ADS, A3:2, BE3:0, WIDTH/HLTD1:0, D/C, W/R, DT/R, DEN, BLAST, LOCK
~
~
~
Valid
Valid
~
~
HOLD
HOLDA
(Note)
NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the same edge in which it recognizes HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly, the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
64
~
~
~
Advance Information Datasheet
Figure 40.
~ ~
CLKIN ~ ~ ~ ~ VCC ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~
~~ ~~
AD31:0, A3:2,D/C ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
Idle (Note 2) Valid Input (Note 3) Valid Output (Note 3) ~ ~ ~ ~
~ ~
HOLD ~ ~ ~ ~ ~ ~ HOLDA ~ ~ LOCK/ ONCE ~ ~ ~~ ~~ STEST ~ ~ RESET ~ ~ ~ ~ ~ ~ ~~~ ~~~ ~ ~
~~ ~~
(Input) ~~~ ~~~ Valid
(Output) ~~~ ~~~
VCC and CLKIN stable to RESET High, minimum 10,000 CLKIN periods, for PLL stabilization.
Built-in self-test (Note 4)
~~ ~~
~~ ~~
~ ~
Advance Information Datasheet
~ ~ ~ ~
Cold Reset Waveform
ALE, ADS, BE3:0, DEN, BLAST ALE,W/R, DT/R WIDTH/HLTD1:0 FAIL
(Note 1)
First Bus Activity
Notes: 1. The processor asserts FAIL during built-in self-test. If self- test passes, the FAIL pin is deasserted.The processor also asserts FAIL during the bus confidence test. If the bus confidence test passes, FAIL is deasserted and the processor begins user program execution. 2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure. 3. Since the bus is idle, hold requests are honored during reset and built-in self-test. 4. When selected, built-in self test requires approximately (in CLKIN periods): 393,000 for 80960JT, 207,000 for 80960JD, and 414,000 for 80960JA/JF.
80960JA/JF/JD/JT 3.3 V Microprocessor
65
~ ~
ALE, ADS, BE3:0, DEN, BLAST ALE, W/R,DT/R, BSTAT, WIDTH/HLTD1:0 ~ ~ FAIL ~ ~ AD31:0, A3:2, D/C ~ ~
~ ~
~ ~
~ ~
~ ~
HOLD
~~~ ~ ~ ~~ ~
HOLDA LOCK/ONCE STEST
~ ~ ~~ ~ ~~ ~ ~ ~~ ~ ~~
Valid ~ ~ Maximum RESET Low to Reset State 4 CLKIN Cycles ~ ~
RESET ~ ~ ~ ~ RESET High to First Bus Activity: Minimum RESET Low Time 15 CLKIN Cycles 80960JT - 26 CLKIN Cycles 80960JD - 46 CLKIN Cycles 80960JA/JF - 92 CLKIN Cycles ~ ~
Advance Information Datasheet
~ ~
~ ~
~~ ~~
~ ~
~ ~
~~ ~~
~~ ~~
66 Warm Reset Waveform
CLKIN
Figure 41.
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 42.
CLKIN may not be allowed to float. It must be driven high or low or continue to run. CLKIN ~ ~ ~ ~ VCC ~ ~ ~ ~ ALE, ADS, BE3:0, DEN, BLAST ~ ~ ALE,W/R, DT/R, WIDTH/HLTD1:0 ~ ~ ~ ~ FAIL ~ ~ ~~ ~~ AD31:0, A3:2, D/C ~ ~ HOLD ~ ~ ~~ ~~ ~~ ~~ ~~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~ ~~
~~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~
~~ ~~
HOLDA ~ ~ ~~ ~~ LOCK/ ONCE ~ ~ STEST ~ ~ RESET ~ ~ ~ ~ ~ ~ (Note 1) VCC and CLKIN stable to RESET High, minimum 10,000 CLKIN periods, for PLL stabilization. ~ ~ ~ ~ (Input) ~~ ~~ ~~~~~ ~~~~~
~ ~
NOTES: 1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET. 2. The ONCE input may be removed after the processor enters ONCE Mode.
~~~~ ~~~~
~ ~
~ ~
~ ~
~ ~
Advance Information Datasheet Entering the ONCE State
80960JA/JF/JD/JT 3.3 V Microprocessor
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80960JA/JF/JD/JT 3.3 V Microprocessor
5.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold (Th). During system operation, the processor continuously enters and exits different bus states. The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address. Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is not ready, the processor can wait as long as necessary for the memory or I/O device to respond. After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word. The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover. The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the bus enters the Ta state to transmit the new address.
Figure 43.
Bus States with Arbitration
(READY AND BURST) OR NOT READY
Tw/Td Ta RECOVERED AND REQUEST PENDING AND (NO HOLD OR LOCKED) READY AND NO BURST
REQUEST PENDING AND (NO HOLD OR LOCKED) REQUEST PENDING AND NO HOLD RECOVERED AND NO REQUEST AND (NO HOLD OR LOCKED) Tr
NOT RECOVERED
NO REQUEST AND (NO HOLD OR LOCKED) Ti ONCE & RESET DEASSERTION
NO REQUEST AND NO HOLD
Th
RECOVERED AND HOLD AND NOT LOCKED
To
RESET HOLD AND NOT LOCKED HOLD -- RDYRCV ASSERTED -- RDYRCV NOT ASSERTED -- BLAST NOT ASSERTED -- BLAST ASSERTED -- RDYRCV NOT ASSERTED -- RDYRCV ASSERTED -- NEW TRANSACTION -- NO NEW TRANSACTION -- HOLD REQUEST ASSERTED -- HOLD REQUEST NOT ASSERTED -- ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS -- NO ATOMIC EXECUTION IN PROGRESS -- RESET ASSERTED -- ONCE ASSERTED
Ti -- IDLE STATE Ta -- ADDRESS STATE Tw / Td -- WAIT/DATA STATE Tr -- RECOVERY STATE Th -- HOLD STATE To -- ONCE STATE
READY NOT READY BURST NO BURST RECOVERED NOT RECOVERED REQUEST PENDING NO REQUEST HOLD NO HOLD LOCKED NOT LOCKED RESET ONCE
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80960JA/JF/JD/JT 3.3 V Microprocessor
5.2
Boundary-Scan Register
The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins. Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that contain "CTL" select the direction of bidirectional pins or HIGHZ output pins. If a "1" is loaded into the control cell, the associated pin(s) are HIGHZ or selected as input.
Table 25.
Boundary-Scan Register Bit Order
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Signal RDYRCV (TDI) HOLD XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 NMI FAIL ALE WIDTH/HLTD1 WIDTH/HLTD0 A2 A3 CONTROL1 CONTROL2 BLAST D/C ADS W/R DT/R Input/ Output I I I I I I I I I I I I O O O O O Enable cell
1
Bit 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Signal DEN HOLDA ALE LOCK/ONCE cell LOCK/ONCE BSTAT BE0 BE1 BE2 BE3 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18
Input/ Output O O O Enable cell1 I/O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Bit 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
Signal AD17 AD16 AD15 AD14 AD13 AD12 AD cells AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CLKIN RESET STEST (TDO)
Input/ Output I/O I/O I/O I/O I/O I/O Enable cell1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I
Enable cell1 O O O O O
NOTE: 1. Enable cells are active low.
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69
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 26.
Natural Boundaries for Load and Store Accesses
Data Width Byte Short Word Word Double Word Triple Word Quad Word Natural Boundary (Bytes) 1 2 4 8 16 16
Table 27.
Summary of Byte Load and Store Accesses
Address Offset from Natural Boundary (in Bytes) +0 (aligned) Accesses on 8-Bit Bus (WIDTH1:0=00) * byte access Accesses on 16 Bit Bus (WIDTH1:0=01) * byte access Accesses on 32 Bit Bus (WIDTH1:0=10) * byte access
Table 28.
Summary of Short Word Load and Store Accesses
Address Offset from Natural Boundary (in Bytes) +0 (aligned) +1 Accesses on 8-Bit Bus (WIDTH1:0=00) * burst of 2 bytes * 2 byte accesses Accesses on 16 Bit Bus (WIDTH1:0=01) * short-word access * 2 byte accesses Accesses on 32 Bit Bus (WIDTH1:0=10) * short-word access * 2 byte accesses
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 29.
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
Address Offset from Natural Boundary in Bytes Accesses on 8-Bit Bus (WIDTH1:0=00) Accesses on 16 Bit Bus (WIDTH1:0=01) * case n=1: burst of 2 short words +0 (aligned) (n =1, 2, 3, 4) * case n=2: burst of 4 short words * n burst(s) of 4 bytes * case n=3: burst of 4 short words burst of 2 short words * case n=4: 2 bursts of 4 short words +1 (n =1, 2, 3, 4) +5 (n = 2, 3, 4) +9 (n = 3, 4) +13 (n = 3, 4) +2 (n =1, 2, 3, 4) +6 (n = 2, 3, 4) +10 (n = 3, 4) +14 (n = 3, 4) +3 (n =1, 2, 3, 4) +7 (n = 2, 3, 4) +11 (n = 3, 4) +15 (n = 3, 4) +4 (n = 2, 3, 4) +8 (n = 3, 4) +12 (n = 3, 4) * n burst(s) of 4 bytes * n burst(s) of 2 short words * n word access(es) * byte access * burst of 2 bytes * n-1 burst(s) of 4 bytes * byte access * burst of 2 bytes * n-1 burst(s) of 4 bytes * burst of 2 bytes * byte access * n-1 burst(s) of 4 bytes * burst of 2 bytes * byte access * byte access * short-word access * n-1 burst(s) of 2 short words * byte access * short-word access * n-1 burst(s) of 2 short words * short-word access * byte access * byte access * short-word access * n-1 word access(es) * byte access * short-word access * n-1 word access(es) * short-word access * byte access * n-1 word access(es) * short-word access * byte access * burst of n word(s) Accesses on 32 Bit Bus (WIDTH1:0=10)
* n-1 burst(s) of 2 short words * short-word access * byte access
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80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 44.
Summary of Aligned and Unaligned Accesses (32-Bit Bus)
Byte Offset 0 4 8 12 16 20 24
Word Offset 0
1
2
3
4
5
6
Short Access (Aligned)
Byte, Byte Accesses Short-Word Load/Store Short Access (Aligned)
Byte, Byte Accesses
Word Access (Aligned) Byte, Short, Byte, Accesses Word Load/Store Short, Short Accesses
Byte, Short, Byte Accesses
One Double-Word Burst (Aligned) Byte, Short, Word, Byte Accesses Short, Word, Short Accesses Double-Word Load/Store Byte, Word, Short, Byte Accesses Word, Word Accesses
One Double-Word Burst (Aligned)
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80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 45.
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
0 Byte Offset 0 1 2 3 4 One Three-Word Burst (Aligned) Byte, Short, Word, Word, Byte Accesses Triple-Word Load/Store Short, Word, Word, Short Accesses Byte, Word, Word, Short, Byte Accesses Word, Word, Word Accesses Word, Word, Word Accesses Word, Word, Word Accesses 5 6 4 8 12 16 20 24
Word Offset
One Four-Word Burst (Aligned) Byte, Short, Word, Word, Word, Byte Accesses Quad-Word Load/Store Short, Word, Word, Word, Short Accesses Byte, Word, Word, Word, Short, Byte Accesses Word, Word, Word, Word Accesses Word, Word, Word, Word, Accesses
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80960JA/JF/JD/JT 3.3 V Microprocessor
6.0
Device Identification
80960Jx processors may be identified electrically, according to device type and stepping (see Figure 46, and Table 31 through Table 36). Table 30 identifies the device type and stepping for all 5V, 80960Jx processors. Figure 46, and Table 31 through Table 36 identify all 3.3V-5V-tolerant 80960Jx processors. The device ID was enhanced to differentiate between 3.3V and 5V supply voltages, and between non-clock-doubled and clock-doubled cores when stepping from the A2 stepping to the C0 stepping. The 32-bit identifier is accessible in three ways:
* Upon reset, the identifier is placed into the g0 register. * The identifier may be accessed from supervisor mode at any time by reading the DEVICEID
register at address FF008710H.
* The IEEE Standard 1149.1 Test Access Port may select the DEVICE ID register through the
IDCODE instruction.
* The device and stepping letter is also printed on the top side of the product package.
Table 30. 80960Jx Device Type and Stepping Reference
Device and Stepping 80960JT A0, A1 80960JD C0 80960JF C0 80960JA C0 Version Number 0000 0011 0011 0011 Part Number 0000 1000 0010 1011 0000 1000 0011 0000 0000 1000 0010 0000 0000 1000 0010 0001 Manufacturer 0000 0001 001 0000 0001 001 0000 0001 001 0000 0001 001 X 1 1 1 1 Complete ID (Hex) 0082B013 30830013 30820013 30821013
Figure 46.
80960JT Device Identification Register
Part Number
Version VCC
Product Type
Gen
Model
Manufacturer ID
1
0
0001
00
0
001
0
10110
0000
00
1
001
1
28
24
20
16
12
8
4
0
74
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 31.
Fields of 80960JT Device ID
Field Version VCC Product Type Value See Table 32 0 = 3.3 V device 000 100 (Indicates i960 CPU) Definition Indicates major stepping changes. Indicates that a device is 3.3 V. Designates type of product. Indicates the generation (or series) the product belongs to. Indicates member within a series and specific model information.
Generation Type 0001 = J-series Model D DPCC D = Clock Multiplier (01) Clock-Tripled (P) Product Derivative (0) Jx C = Cache Size (11) 16K I-cache, 4K D-cache Manufacturer ID 000 0000 1001 (Indicates Intel)
Manufacturer ID assigned by IEEE.
Table 32.
80960JT Device ID Model Types
Device 80960JT A0, A1 Version 0000 VCC 0 Product 000100 Gen. 0001 Model 01011 Manufacturer ID 00000001001 `1' 1
Figure 47.
80960JD Device Identification Register
Part Number
Version VCC
Product Type
Gen
Model
Manufacturer ID
1
0
0001
00
0
001
1
00010
0000
00
1
001
1
28
24
20
16
12
8
4
0
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80960JA/JF/JD/JT 3.3 V Microprocessor
Table 33.
Fields of 80960JD Device ID
Field Version VCC Product Type Generation Type Value See Table 30 0 = 3.3 V device 1 = 5V device 00 0100 (Indicates i960 CPU) 0001 = J-series D000C D = Clock Doubled (0) Not Clock-Doubled (1) Clock Doubled Model C = Cache Size (0) 4K I-cache, 2K D-cache (1) 2K I-cache, 1K D-cache Manufacturer ID 000 0000 1001 (Indicates Intel) Manufacturer ID assigned by IEEE. Indicates member within a series and specific model information. Definition Indicates major stepping changes. Indicates that a device is 3.3 V. Designates type of product. Indicates the generation (or series) the product belongs to.
Table 34.
80960JD Device ID Model Types
Device 80960JD C0 Version 0011 VCC 0 Product 000100 Gen. 0001 Model 10000 Manufacturer ID 00000001001 `1' 1
Figure 48.
80960JA/JF Device Identification Register
Part Number
Version VCC
Product Type
Gen
Model
Manufacturer ID
1
0
0001
00
0
001
0
0000
00
1
001
1
28
24
20
16
12
8
4
0
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Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 35.
Fields of 80960JA/JF Device ID
Field Version VCC Product Type Generation Type Model See Table 36 0 = 3.3 V device 1 = 5V device 00 0100 (Indicates i960 CPU) 0001 = J-series 0000C C = Cache Size 0 = 4K I-cache, 2K D-cache 1 = 2K I-cache, 1K D-cache Manufacturer ID 000 0000 1001 (Indicates Intel) Manufacturer ID assigned by IEEE. Designates type of product. Indicates the generation (or series) to which the product belongs. Indicates member within a series and specific model information. Value Definition Indicates major stepping changes. Indicates that a device is 3.3 V.
Table 36.
80960JA/JF Device ID Model Types
Device 80960JA C0 80960JF C0 Version 0011 0011 VCC 0 0 Product 000100 000100 Gen. 0001 0001 Model 00001 00000 Manufacturer ID 00000001001 00000001001 `1' 1 1
7.0
Revision History
This data sheet supersedes revisions 273109-001, 272971-002, and 276146-001. Table 37 indicates significant changes since the previous revisions.
Table 37.
Data Sheet Revision History
Figure 1 "80960Jx Microprocessor Package Options" on page 7 Section 3.1.4, "80960Jx 196-Ball MPBGA Pinout" on page 29 Figure 12 "TLX vs. AD Bus Load Capacitance" on page 48 Throughout document Added MPBGA package diagram Added new Figures 6 and 7, Tables 10, 11 and 13 Added with following note Merged 80960JA/JF/JD/JT 3.3 volt Processor data sheets
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